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| _______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. +2.7v to +5.25v, low-power, 8-channel, serial 10-bit adcs max148/max149 general description the max148/max149 10-bit data-acquisition systems combine an 8-channel multiplexer, high-bandwidth track/hold, and serial interface with high conversion speed and low power consumption. they operate from a single +2.7v to +5.25v supply, and sample to 133ksps. both devices analog inputs are software configurable for unipolar/bipolar and single-ended/differential operation. the 4-wire serial interface connects directly to spi k / qspi k and microwire k devices without external logic. a serial-strobe output allows direct connection to tms320-family digital signal processors. the max148/ max149 use either the internal clock or an external seri - al-interface clock to perform successive-approximation analog-to-digital conversions. the max149 has an internal 2.5v reference, while the max148 requires an external reference. both parts have a reference-buffer amplifier with a q 1.5% voltage- adjustment range. these devices provide a hard-wired shdn pin and a software-selec table power-down, and can be pro - grammed to automatically shut down at the end of a conversion. accessing the serial interface automatically powers up the max148/max149, and the quick turn-on time allows them to be shut down between all conver - sions. this technique can cut supply current to under 60 f a at reduced sampling rates. the max148/max149 are available in a 20-pin dip and a 20-pin ssop. for 4-channel versions of these devices, see the max1248/max1249 data sheet. applications por table data logging data acquisition medical instruments battery-powered instruments pen digitizers process control features s 8-channel single-ended or 4-channel differential inputs s single-supply operation: +2.7v to +5.25v s internal 2.5v reference (max149) s low power: 1.2ma (133ksps, 3v supply) 54a (1ksps, 3v supply) 1a (power-down mode) s spi/qspi/microwire/tms320-compatible 4-wire serial interface s software-configurable unipolar or bipolar inputs s 20-pin dip/ssop packages 19-0464; rev 4; 1/10 ordering information ordering information continued at end of data sheet. ? contact factory for availability of alternate surface-mount package. specify lead-free by placing + by the part number when ordering. * contact factory for availability of cerdip package, and for processing to mil-std-883b. not available in lead-free. pin configuration appears at end of data sheet. spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. part ? temp range pin- package inl (lsb) max148 acpp 0c to +70c 20 plastic dip 1/2 max148bcpp 0c to +70c 20 plastic dip 1 max148acap 0c to +70c 20 ssop 1/2 max148bcap 0c to +70c 20 ssop 1 typical operating circuit cpu v dd v ss v dd dgnd agnd com sclk din dout sstrb readj vref ch7 ch0 +3v 0.1ff 4.7ff o to +2.5v analog inputs 0.01ff i/o sck (sk) mosi (so) miso (si) max149 cs shdn
+2.7v to +5.25v, low-power, 8-channel, serial 10-bit adcs max148/max149 2 ______________________________________________________________________________________ stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to agnd, dgnd .............................................. -0.3v to +6v agnd to dgnd ................................................... -0.3v to +0.3v ch0Cch7, com to agnd, dgnd ........... -0.3v to (v dd + 0.3v) vref, refadj to agnd ........................... -0.3v to (v dd + 0.3v) digital inputs to dgnd ........................................... -0.3v to +6v digital outputs to dgnd .......................... -0.3v to (v dd + 0.3v) digital output sink current ................................................ 25ma continuous power dissipation (t a = +70 n c) plastic dip (derate 11.11mw/ n c above +70 n c) .......... 889mw ssop (derate 8.00mw/ n c above +70 n c) .................... 640mw cerdip (derate 11.11mw/ n c above +70 n c) .............. 889mw operating temperature ranges max148_c_p/max149_c_p .............................. 0 n c to +70 n c max148_e_p/max149_e_p ............................ -40 n c to +85 n c max148_mjp/max149_mjp ........................ -55 n c to +125 n c max149bmap ............................................... -55 n c to +125 n c storage temperature range ............................ -60 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c electrical characteristics ( v dd = +2.7v to +5.25v; com = 0; f sclk = 2.0mhz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); max1494.7 f f capacitor at vref pin; max148external reference, vref = 2.500v applied to vref pin; t a = t min to t max , unless otherwise noted.) absolute maximum ratings parameter symbol conditions min typ max units dc accuracy (note 1) resolution 10 bits relative accuracy (note 2) inl max14_a 0.5 lsb max14_b 1.0 differential nonlinearity dnl no missing codes over temperature 1 lsb offset error max14_a 0.15 1 lsb max14_b 0.15 2 gain error (note 3) max14_a 1 lsb max14_b 2 gain temperature coefficient 0.25 ppm/ c channel-to-channel offset matching 0.05 lsb dynamic specifications (10khz sine-wave input, 0 to 2.500v p-p , 133ksps, 2.0mhz external clock, bipolar input mode) signal-to-noise + distortion noise sinad 66 db total harmonic distortion thd up to the 5th harmonic -70 db spurious-free dynamic range sfdr 70 db channel-to-channel crosstalk 65khz, 2.500v p-p (note 4) -75 db small-signal bandwidth -3db rolloff 2.25 mhz full-power bandwidth 1.0 mhz conversion rate conversion time (note 5) t conv internal clock, shdn = unconnected 5.5 7.5 s internal clock, shdn = v dd 35 65 external clock = 2mhz, 12 clocks/ conversion 6 track/hold acquisition time t acq 1.5 s aperture delay 30 ns aperture jitter < 50 ps +2.7v to +5.25v, low-power, 8-channel, serial 10-bit adcs max148/max149 _______________________________________________________________________________________ 3 electrical characteristics (continued) ( v dd = +2.7v to +5.25v; com = 0; f sclk = 2.0mhz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); max1494.7 f f capacitor at vref pin; max148external reference, vref = 2.500v applied to vref pin; t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units conversion rate (continued) internal clock frequency shdn = unconnected 1.8 mhz shdn = v dd 0.225 external clock frequency 0.1 2.0 mhz data transfer only 1 2.0 analog/com inputs input voltage range, single- ended and differential (note 6) unipolar, com = 0 0 to vref v bipolar, com = vref/2 vref/2 multiplexer leakage current on/off leakage current, v ch_ = 0 or v dd 0.01 1 a input capacitance 16 pf internal reference (max149 only, reference buffer enabled) vref output voltage t a = +25 c (note 7) 2.470 2.500 2.530 v vref short-circuit current 30 ma vref temperature coefficient max149 30 ppm/ c load regulation (note 8) 0 to 0.2ma output load 0.35 mv capacitive bypass at vref internal compensation mode 0 f external compensation mode 4.7 capacitive bypass at refadj 0.01 f refadj adjustment range 1.5 % external reference at vref (buffer disabled) vref input voltage range (note 9) 1.0 v dd + 50mv v vref input current vref = 2.500v 100 150 a vref input resistance 18 25 k? shutdown vref input current 0.01 10 a refadj buffer-disable threshold v dd - 0.5 v external reference at refadj capacitive bypass at vref internal compensation mode 0 f external compensation mode 4.7 reference buffer gain max149 2.06 v/v max148 2.00 refadj input current max149 50 a max148 10 +2.7v to +5.25v, low-power, 8-channel, serial 10-bit adcs max148/max149 4 ______________________________________________________________________________________ electrical characteristics (continued) ( v dd = +2.7v to +5.25v; com = 0; f sclk = 2.0mhz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); max1494.7 f f capacitor at vref pin; max148external reference, vref = 2.500v applied to vref pin; t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units digital inputs (din, sclk, cs , shdn ) din, sclk, cs input high voltage v ih v dd 3.6v 2.0 v v dd > 3.6v 3.0 din, sclk, cs input low voltage v il 0.8 v din, sclk, cs input hysteresis v hyst 0.2 v din, sclk, cs input leakage i in v in = 0 or v dd 0.01 1 a din, sclk, cs input capacitance c in (note 10) 15 pf shdn input high voltage v sh v dd - 0.4 v shdn input mid voltage v sm 1.1 v dd - 1.1 v shdn input low voltage v sl 0.4 v shdn input current i s shdn = 0 or v dd 4.0 a shdn voltage, unconnected v flt shdn = unconnected v dd /2 v shdn maximum allowed leakage, mid input shdn = unconnected 100 na digital outputs (dout, sstrb) output-voltage low v ol i sink = 5ma 0.4 v i sink = 16ma 0.8 output-voltage high v oh i source = 0.5ma v dd - 0.5 v three-state leakage current i l cs = v dd 0.01 10 a three-state output capacitance c out cs = v dd (note 10) 15 pf power requirements positive supply voltage v dd 2.70 5.25 v positive supply current i dd operating mode, full-scale input (note 11) v dd = 5.25v 1.6 3.0 ma v dd = 3.6v 1.2 2.0 full power-down v dd = 5.25v 3.5 15 a v dd = 3.6v 1.2 10 fast power-down (max149) 30 70 supply rejection (note 12) psr full-scale input, external reference = 2.500v, v dd = 2.7v to 5.25v 0.3 mv +2.7v to +5.25v, low-power, 8-channel, serial 10-bit adcs max148/max149 _______________________________________________________________________________________ 5 timing characteristics ( v dd = +2.7v to +5.25v, t a = t min to t max , unless otherwise noted.) note 1: tested at v dd = 2.7v; com = 0; unipolar single-ended input mode. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. note 3: max149internal reference, offset nulled; max148external reference (v ref = +2.500v), offset nulled. note 4: ground on channel; sine wave applied to all off channels. note 5: conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. note 6: the common-mode range for the analog inputs is from agnd to v dd . note 7: sample tested to 0.1% aql. note 8: external load should not change during conversion for specified accuracy. note 9: adc performance is limited by the converters noise floor, typically 300 f v p-p . note 10: guaranteed by design. not subject to production testing. note 11: the max148 typically draws 400 f a less than the values shown. note 12: measured as |v fs (2.7v) - v fs (5.25v)|. parameter symbol conditions min typ max units acquisition time t acq 1.5 s din to sclk setup t ds 100 ns din to sclk hold t dh 0 ns sclk fall to output data valid t do figure 1 max14_ _c/e 20 200 ns max14_ _m 20 240 cs fall to output enable t dv figure 1 240 ns cs rise to output disable t tr figure 2 240 ns cs to sclk rise setup t css 100 ns cs to sclk rise hold t csh 0 ns sclk pulse width high t ch 200 ns sclk pulse width low t cl 200 ns sclk fall to sstrb t sstrb figure 1 240 ns cs fall to sstrb output enable t sdv external clock mode only, figure 1 240 ns cs rise to sstrb output disable t str external clock mode only, figure 2 240 ns sstrb rise to sclk rise t sck internal clock mode only (note 7) 0 ns +2.7v to +5.25v, low-power, 8-channel, serial 10-bit adcs max148/max149 6 ______________________________________________________________________________________ typical operating characteristics (v dd = 3.0v, vref = 2.500v, f sclk = 2.0mhz, c load = 20pf, t a = +25 n c, unless otherwise noted.) integral nonlinearity vs. code max148-max149 toc01 code inl (lsb) 768 512 256 -0.10 -0.05 0 0.05 0.10 0 1024 integral nonlinearity vs. supply voltage max148-max149 toc02 supply voltage (v) inl (lsb) 4.75 4.25 3.75 3.25 2.75 0.025 0.050 0.075 0.100 0.125 0 2.25 5.25 max149 max148 integral nonlinearity vs. temperature max148-max149 toc03 temperature (nc) inl (lsb) 100 60 -20 20 0.025 0.050 0.075 0.100 0.125 0 -60 140 max149 max148 v dd = 2.7v supply current vs. supply voltage max148-max149 toc04 supply voltage (v) supply current (ma) 4.75 4.25 3.75 3.25 2.75 0.75 1.00 1.25 1.50 1.75 2.00 0.50 2.25 5.25 rl = j code = 1010101000 max149 max148 c load = 50pf c load = 20pf shutdown supply current vs. supply voltage max148-max149 toc05 supply voltage (v) shutdown supply current (fa) 4.75 4.25 3.75 3.25 2.75 0.5 1.0 1.5 2.0 2.5 3.0 0 2.25 5.25 full power-down max149 internal reference voltage vs. supply voltage max148-max149 toc06 supply voltage (v) internal reference voltage (v) 4.75 4.25 3.75 3.25 2.75 2.4995 2.5000 2.5005 2.5010 2.5015 2.5020 2.4990 2.25 5.25 supply current vs. temperature max148-max149 toc07 temperature (nc) supply current (ma) 100 60 20 -20 0.9 1.0 1.1 1.2 1.3 0.8 -60 140 r l0ad = j code = 1010101000 max149 max148 shutdown current vs. temperature max148-max149 toc08 temperature (nc) shutdown current (ma) 100 60 20 -20 0.4 0.8 1.2 1.6 2.0 0 -60 140 max149 internal reference voltage vs. temperature max148-max149 toc09 temperature (nc) internal reference voltage (v) 100 60 20 -20 2.495 2.496 2.497 2.498 2.499 2.500 2.501 2.494 -60 140 v dd = 5.25v v dd = 2.7v v dd = 3.6v +2.7v to +5.25v, low-power, 8-channel, serial 10-bit adcs max148/max149 _______________________________________________________________________________________ 7 pin description figure 1. load circuits for enable time figure 2. load circuits for disable time pin name function 1C8 ch0Cch7 sampling analog inputs 9 com ground reference for analog inputs. com sets zero-code voltage in single-ended mode. must be stable to 0.5 lsb. 10 shdn three-level shutdown input. pulling shdn low shuts the max148/max149 down; otherwise, they are fully operational. pulling shdn high puts the reference-buffer amplifier in internal compensation mode. leaving shdn unconnected puts the reference-buffer amplifier in external compensation mode. 11 vref reference-buffer output/adc reference input. reference voltage for analog-to-digital conversion. in internal reference mode (max149 only), the reference buffer provides a 2.500v nominal output, externally adjustable at refadj. in external reference mode, disable the internal buffer by pulling refadj to v dd . 12 refadj input to the reference-buffer amplifier. to disable the reference-buffer amplifier, tie refadj to v dd . 13 agnd analog ground 14 dgnd digital ground 15 dout serial-data output. data is clocked out at sclks falling edge. high impedance when cs is high. 16 sstrb serial-strobe output. in internal clock mode, sstrb goes low when the max148/max149 begin the a/d conversion, and goes high when the conversion is finished. in external clock mode, sstrb pulses high for one clock period before the msb decision. high impedance when cs is high (external clock mode). 17 din serial-data input. data is clocked in at sclks rising edge. 18 cs active-low chip select. data will not be clocked into din unless cs is low. when cs is high, dout is high impedance. 19 sclk serial-clock input. clocks data in and out of serial interface. in external clock mode, sclk also sets the conversion speed (duty cycle must be 40% to 60%). 20 v dd positive supply voltage a) high-z to v oh and v ol to v oh b) high-z to v ol and v oh to v ol dout dgnd 6ki v dd dgnd dout 6ki c load 50pf c load 50pf b) v ol to high-z a) v oh to high-z dout dgnd 6ki c load 50pf v dd dout dgnd 6ki c load 50pf +2.7v to +5.25v, low-power, 8-channel, serial 10-bit adcs max148/max149 8 ______________________________________________________________________________________ detailed description the max148/max149 analog-to-digital converters (adcs) use a successive-approximation conversion technique and input track/hold (t/h) circuitry to convert an analog signal to a 10-bit digital output. a flexible serial interface provides easy interface to microproces - sors ( f ps). figure 3 is a block diagram of the max148/ max149. pseudo-differential input the sampling architecture of the adcs analog com - parator is illustrated in the equivalent input circuit (figure 4). in single-ended mode, in+ is internally switched to ch0Cch7, and in- is switched to com. in differential mode, in+ and in- are selected from the following pairs: ch0/ch1, ch2/ch3, ch4/ch5, and ch6/ch7. configure the channels with tables 2 and 3. in differential mode, in- and in+ are internally switched to either of the analog inputs. this configuration is pseudo-differential to the effect that only the signal at in+ is sampled. the return side (in-) must remain stable within q 0.5 lsb ( q 0.1 lsb for best results) with respect to agnd during a conversion. to accomplish this, con - nect a 0.1 f f capacitor from in- (the selected analog input) to agnd. during the acquisition interval, the channel selected as the positive input (in+) charges capacitor c hold . the acquisition interval spans three sclk cycles and ends on the falling sclk edge after the last bit of the input control word has been entered. at the end of the acquisi - tion interval, the t/h switch opens, retaining charge on c hold as a sample of the signal at in+. the conversion interval begins with the input multiplexer switching c hold from the positive input (in+) to the negative input (in-). in single-ended mode, in- is simply com. this unbalances node zero at the comparators input. the capacitive dac adjusts during the remainder of the conversion cycle to restore node zero to 0 within the limits of 10-bit resolution. this action is equivalent to transferring a 16pf x [(v in+ ) - (v in- )] charge from c hold to the binary-weighted capacitive dac, which in turn forms a digital representation of the analog input signal. track/hold the t/h enters its tracking mode on the falling clock edge after the fifth bit of the 8-bit control word has been shifted in. it enters its hold mode on the falling clock edge after the eighth bit of the control word has been shifted in. if the converter is set up for single-ended inputs, in- is connected to com, and the converter samples the + input. if the converter is set up for dif - ferential inputs, in- connects to the - input, and the difference of |in+ - in-| is sampled. at the end of the conversion, the positive input connects back to in+, and c hold charges to the input signal. the time required for the t/h to acquire an input signal is a function of how quickly its input capacitance is charged. if the input signals source impedance is high, the acquisition time lengthens, and more time must be figure 3. block diagram figure 4. equivalent input circuit cs shdn sclk din ch0 1 18 15 16 20 14 13 19 input shift register output shift register analog input mux clock in 10+2-bit sar adc +1.21v reference (max149) ref out t/h control logic int clock 17 10 2 3 4 5 6 7 8 9 12 11 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dout sstrb v dd dgnd agnd +2.500v 20k? *a 2.00 (max148) a 2.06* refadj vref max148 max149 com ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 single-ended mode: in+ = ch0?ch7, in- = com. differential mode: in+ and in- selected from pairs of ch0/ch1, ch2/ch3, ch4/ch5, and ch6/ch7. at the sampling instant, the mux input switches from the selected in+ channel to the selected in- channel. comparator capacitive dac c switch track t/h switch r in 9k? c hold hold vref zero 16pf input mux - + +2.7v to +5.25v, low-power, 8-channel, serial 10-bit adcs max148/max149 _______________________________________________________________________________________ 9 allowed between conversions. the acquisition time, t acq , is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired. it is calculated by the following equation: t acq = 7 x (r s + r in ) x 16pf where r in = 9k i , r s = the source impedance of the input signal, and t acq is never less than 1.5 f s. note that source impedances below 4k i do not significantly affect the adcs ac performance. higher source impedances can be used if a 0.01 f f capacitor is connected to the individual analog inputs. note that the input capacitor forms an rc filter with the input source impedance, limiting the adcs signal bandwidth. input bandwidth the adcs input tracking circuitry has a 2.25mhz small-signal bandwidth, so it is possible to digitize high- speed transient events and measure periodic signals with bandwidths exceeding the adcs sampling rate by using undersampling techniques. to avoid high- frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. analog input protection internal protection diodes, which clamp the analog input to v dd and agnd, allow the channel input pins to swing from agnd - 0.3v to v dd + 0.3v without damage. however, for accurate conversions near full scale, the inputs must not exceed v dd by more than 50mv or be lower than agnd by 50mv. if the analog input exceeds 50mv beyond the sup - plies, do not forward bias the protection diodes of off channels over 2ma. quick look to quickly evaluate the max148/max149s analog per - formance, use the circuit of figure 5. the max148/ max149 require a control byte to be written to din before each conversion. tying din to +3v feeds in control bytes of $ff (hex), which trigger single-ended unipolar conversions on ch7 in external clock mode without powering down between conversions. in external clock mode, the sstrb output pulses high for one clock period before the most significant bit of the conversion result is shifted out of dout. varying the analog input to ch7 will alter the sequence of bits from dout. a total of 15 clock cycles is required per conversion. all transitions of the sstrb and dout outputs occur on the falling edge of sclk. figure 5. quick-look circuit max148 max149 0.1f v dd dgnd agnd com sclk din dout sstrb +3v n.c. 0.01f ch7 +3v refadj vref c1 0.1f 0 to +2.500v analog input oscilloscope ch1 ch2 ch3 ch4 *full-scale analog input, conversion result = $fff (hex) optional for max149, required for max148 +3v 2mhz oscillator sclk sstrb dout* 2.5v 1000pf comp v out +3v max872 shdn cs +2.7v to +5.25v, low-power, 8-channel, serial 10-bit adcs max148/max149 10 _____________________________________________________________________________________ table 1. control-byte format table 2. channel selection in single-ended mode (sgl/ dif = 1) how to start a conversion start a conversion by clocking a control byte into din. with cs low, each rising edge on sclk clocks a bit from din into the max148/max149s internal shift register. after cs falls, the first arriving logic 1 bit defines the control bytes msb. until this first start bit arrives, any number of logic 0 bits can be clocked into din with no effect. table 1 shows the control-byte format. the max148/max149 are compatible with spi/qspi and microwire devices. for spi, select the correct clock polarity and sampling edge in the spi control registers: set cpol = 0 and cpha = 0. microwire, spi, and qspi all transmit a byte and receive a byte at the same time. using the typical operating circuit , the simplest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the adc, and two more 8-bit transfers to clock out the conversion result). see figure 20 for max148/ max149 qspi connections. bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) start sel2 sel1 sel0 uni/ bip sgl// dif pd1 pd0 bit name description 7(msb) start the first logic 1 bit after cs goes low defines the beginning of the control byte. 6 5 4 sel2 sel1 sel0 these three bits select which of the eight channels are used for the conversion (tables 2 and 3) 3 uni/ bip 1 = unipolar, 0 = bipolar. selects unipolar or bipolar conversion mode. in unipolar mode, an analog input signal from 0 to vref can be converted; in bipolar mode, the signal can range from -vref/2 to +vref/2. 2 sgl/ dif 1 = single ended, 0 = differential. selects single-ended or differential conversions. in single- ended mode, input signal voltages are referred to com. in differential mode, the voltage difference between two channels is measured (tables 2 and 3). 1 pd1 selects clock and power-down modes. 0(lsb) pd0 pd1 pd0 mode 0 0 full power-down 0 1 fast power-down (max149 only) 1 0 internal clock mode 1 1 external clock mode sel2 sel1 sel0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com 0 0 0 + - 1 0 0 + - 0 0 1 + - 1 0 1 + - 0 1 0 + - 1 1 0 + - 0 1 1 + - 1 1 1 + - +2.7v to +5.25v, low-power, 8-channel, serial 10-bit adcs max148/max149 ______________________________________________________________________________________ 11 table 3. channel selection in differential mode (sgl/ dif = 0) figure 6. 24-clock external clock mode conversion timing (microwire and spi-compatible, qspi-compatible with f sclk p 2mhz) simple software interface make sure the cpus serial interface runs in master mode so the cpu generates the serial clock. choose a clock frequency from 100khz to 2mhz. 1) set up the control byte for external clock mode and call it tb1. tb1 should be of the format: 1xxxxx11 binary, where the xs denote the particular channel and conversion mode selected. 2) use a general-purpose i/o line on the cpu to pull cs low. 3) transmit tb1 and, simultaneously, receive a byte and call it rb1. ignore rb1. 4) transmit a byte of all zeros ($00 hex) and, simultane - ously, receive byte rb2. 5) transmit a byte of all zeros ($00 hex) and, simultane - ously, receive byte rb3. 6) pull cs high. figure 6 shows the timing for this sequence. bytes rb2 and rb3 contain the result of the conversion, padded with one leading zero, two sub-lsb bits, and three trailing zeros. the total conversion time is a function of the serial-clock frequency and the amount of idle time between 8-bit transfers. to avoid excessive t/h droop, make sure the total conversion time does not exceed 120 f s. digital output in unipolar input mode, the output is straight binary (figure 17). for bipolar input mode, the output is twos complement (figure 18). data is clocked out at the fall - ing edge of sclk in msb-first format. clock modes the max148/max149 may use either an external serial clock or the internal clock to perform the successive- approximation conversion. in both clock modes, the exter - nal clock shifts data in and out of the max148/max149. sel2 sel1 sel0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 0 0 0 + - 0 0 1 + - 0 1 0 + - 0 1 1 + - 1 0 0 - + 1 0 1 - + 1 1 0 - + 1 1 1 - + 1 4 8 12 16 20 24 start sel2 sel1 sel0 uni/ bip sgl/ dif pd1 pd0 b9 msb b8 b7 b6 b5 b4 b3 b2 b1 s0 s1 b0 lsb filled with zeros rb1 rb2 idle conversion rb3 acquisition (f sclk = 2mhz) idle 1.5fs sclk t acq din sstrb dout a/d state cs +2.7v to +5.25v, low-power, 8-channel, serial 10-bit adcs max148/max149 12 _____________________________________________________________________________________ figure 7. detailed serial-interface timing figure 8. external clock mode sstrb detailed timing the t/h acquires the input signal as the last three bits of the control byte are clocked into din. bits pd1 and pd0 of the control byte program the clock mode. figures 7C10 show the timing characteristics common to both modes. external clock in external clock mode, the external clock not only shifts data in and out, but it also drives the analog-to-digital conversion steps. sstrb pulses high for one clock period after the last bit of the control byte. successive- approxi - mation bit decisions are made and appear at dout on each of the next 12 sclk falling edges (figure 6). sstrb and dout go into a high-impedance state when cs goes high; after the next cs falling edge, sstrb outputs a logic-low. figure 8 shows the sstrb timing in external clock mode. the conversion must complete in some minimum time, or droop on the sample-and-hold capacitors may degrade conversion results. use internal clock mode if the serial- clock frequency is less than 100khz, or if serial-clock interruptions could cause the conversion interval to exceed 120 f s. t do sclk din dout cs t css t ds t dh t dv t tr t csh t cl t ch t csh pd0 clocked in sclk t sstrb ssrtb cs t sdv t str t sstrb +2.7v to +5.25v, low-power, 8-channel, serial 10-bit adcs max148/max149 ______________________________________________________________________________________ 13 figure 9. internal clock mode timing internal clock in internal clock mode, the max148/max149 generate their own conversion clocks internally. this frees the f p from the burden of running the sar conversion clock and allows the conversion results to be read back at the processors convenience, at any clock rate from 0 to 2mhz. sstrb goes low at the start of the conversion and then goes high when the conversion is complete. sstrb is low for a maximum of 7.5 f s ( shdn = uncon - nected), during which time sclk should remain low for best noise performance. an internal register stores data when the conversion is in progress. sclk clocks the data out of this regis - ter at any time after the conversion is complete. after sstrb goes high, the next falling clock edge produces the msb of the conversion at dout, followed by the remaining bits in msb-first format (figure 9). cs does not need to be held low once a conversion is started. pulling cs high prevents data from being clocked into the max148/max149 and three-states dout, but it does not adversely affect an internal clock mode con - version already in progress. when internal clock mode is selected, sstrb does not go into a high-impedance state when cs goes high. figure 10 shows the sstrb timing in internal clock mode. in this mode, data can be shifted in and out of the max148/max149 at clock rates exceeding 2.0mhz if the minimum acquisition time (t acq ) is kept above 1.5 f s. data framing the falling edge of cs does not start a conversion. the first logic high clocked into din is interpreted as a start bit and defines the first bit of the control byte. a conver - sion starts on sclks falling edge, after the eighth bit of figure 10. internal clock mode sstrb detailed timing 1 sel2 sel1 sel0 pd0 pd1 sgl/ dif uni/ bip 2 3 4 5 6 7 8 9 10 b9 msb b8 b7 b0 lsb s1 s0 11 12 18 19 20 21 22 23 24 sclk din start sstrb 1.5fs 7.5fs max dout ad state idle idle acquisition conversion t conv filled with zeros cs (f sclk = 2mhz)(shdn = unconnected) sstrb sclk note: for best noise performance, keep sclk low during conversion. dout pd0 clock in t sstrb t conv t csh t sck t css t d0 cs +2.7v to +5.25v, low-power, 8-channel, serial 10-bit adcs max148/max149 14 _____________________________________________________________________________________ table 4. typical power-up delay times the control byte (the pd0 bit) is clocked into din. the start bit is defined as follows: the first high bit clocked into din with cs low any time the converter is idle; e.g., after v dd is applied. or the first high bit clocked into din after bit 3 of a con - version in progress is clocked onto the dout pin. if cs is toggled before the current conversion is com - plete, the next high bit clocked into din is recognized as a start bit; the current conversion is terminated, and a new one is started. the fastest the max148/max149 can run with cs held low between conversions is 15 clocks per conversion. figure 11a shows the serial-interface timing necessary to perform a conversion every 15 sclk cycles in exter - nal clock mode. if cs is tied low and sclk is continuous, guarantee a start bit by first clocking in 16 zeros. most microcontrollers ( f cs) require that conversions occur in multiples of 8 sclk clocks; 16 clocks per con - version is typically the fastest that a f c can drive the max148/max149. figure 11b shows the serialinterface timing necessary to perform a conversion every 16 sclk cycles in external clock mode. applications information power-on reset when power is first applied, and if shdn is not pulled low, internal power-on reset circuitry activates the max148/max149 in internal clock mode, ready to con - vert with sstrb = high. after the power supplies stabi - lize, the internal reset time is 10 f s, and no conversions should be performed during this phase. sstrb is high on power-up and, if cs is low, the first logical 1 on din is interpreted as a start bit. until a conversion takes place, dout shifts out zeros. also see table 4. reference-buffer compensation in addition to its shutdown function, shdn selects inter - nal or external compensation. the compensation affects both power-up time and maximum conversion speed. the 100khz minimum clock rate is limited by droop on the sample-and-hold and is independent of the compen - sation used. unconnect shdn to select external compensation. the typical operating circuit uses a 4.7 f f capacitor at vref. a 4.7 f f value ensures reference-buffer stability and allows converter operation at the 2mhz full clock speed. external compensation increases power-up time (see the choosing power-down mode section and table 4). pull shdn high to select internal compensation. internal compensation requires no external capacitor at vref and allows for the shortest power-up times. the maxi - mum clock rate is 2mhz in internal clock mode and 400khz in external clock mode. choosing power-down mode you can save power by placing the converter in a low- current shutdown state between conversions. select full power-down mode or fast power-down mode via bits 1 and 0 of the din control byte with shdn high or uncon - nected (tables 1 and 5). in both software power-down modes, the serial interface remains operational, but the adc does not convert. pull shdn low at any time to shut down the converter completely. shdn overrides bits 1 and 0 of the control byte. full power-down mode turns off all chip functions that draw quiescent current, reducing supply current to 2 f a (typ). fast power-down mode turns off all circuitry except the bandgap reference. with fast power-down mode, the supply current is 30 f a. power-up time can be shortened to 5 f s in internal compensation mode. table 4 shows how the choice of reference-buffer com - pensation and power-down mode affects both power-up reference buffer reference- buffer compensation mode vref capacitor (f) power-down mode power-up delay (s) maximum sampling rate (ksps) enabled internal fast 5 26 enabled internal full 300 26 enabled external 4.7 fast see figure 14c 133 enabled external 4.7 full see figure 14c 133 disabled fast 2 133 disabled full 2 133 +2.7v to +5.25v, low-power, 8-channel, serial 10-bit adcs max148/max149 ______________________________________________________________________________________ 15 delay and maximum sample rate. in external compensa - tion mode, power-up time is 20ms with a 4.7 f f com - pensation capacitor when the capacitor is initially fully discharged. from fast power-down, startup time can be eliminated by using low-leakage capacitors that do not discharge more than ? lsb while shut down. in power- down, leakage currents at vref cause droop on the reference bypass capacitor. figures 12a and 12b show the various power-down sequences in both external and internal clock modes. figure 11a. external clock mode, 15 clocks/conversion timing figure 11b. external clock mode, 16 clocks/conversion timing figure 12a. timing diagram power-down modes, external clock sclk din dout cs s control byte 0 control byte 1 s conversion result 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 s1 s0 conversion result 1 sstrb b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 s1 s0 control byte 2 s 1 8 1 15 15 8 1 sclk din dout cs s 1 8 16 1 8 16 control byte 0 control byte 1 s conversion result 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 s1 s0 b9 b8 b7 b6 conversion result 1 10 + 2 data bits 10 + 2 data bits invalid data valid data external external s x x x x x 1 1 s 0 0 x x x x x x x x x x s 1 1 software power-down mode dout din clock mode shdn sets external clock mode sets external clock mode sets software power-down powered up powered up hardware power-down powered up +2.7v to +5.25v, low-power, 8-channel, serial 10-bit adcs max148/max149 16 _____________________________________________________________________________________ figure 12b. timing diagram power-down modes, internal clock table 5. software power-down and clock mode table 6. hard-wired power-down and internal clock frequency figure 13. average supply current vs. conversion rate with external reference figure 14a. max149 supply current vs. conversion rate, fullpd internal data valid conversion sets internal clock mode sets power-down data valid conversion powered up clock mode din dout sstrb mode power-down powered off s x x x x x 1 0 5 x x x x x 0 0 s pd1 pd0 device mode 0 0 full power-down 0 1 fast power-down 1 0 internal clock 1 1 external clock shdn state device mode reference buffer compensation internal clock frequency 1 enabled internal 225khz unconnected enabled external 1.8mhz 0 power- down average supply current vs. conversion rate with external reference max148/9-f13 conversion rate (hz) average supply current (a) 100k 10k 1k 100 10 1 1 10 100 1000 10,000 0.1 0.1 1m vref = v dd = 3.0v r load = code = 1010101000 8 channels 1 channel average supply current vs. conversion rate (using fullpd) max148/9-f14a conversion rate (hz) average supply current (a) 0.1 1 10 100 10 100 1 0.01 1k r load = code = 1010101000 8 channels 1 channel +2.7v to +5.25v, low-power, 8-channel, serial 10-bit adcs max148/max149 ______________________________________________________________________________________ 17 software power-down software power-down is activated using bits pd1 and pd0 of the control byte. as shown in table 5, pd1 and pd0 also specify the clock mode. when software shut - down is asserted, the adc operates in the last specified clock mode until the conversion is complete. then the adc powers down into a low quiescent-current state. in internal clock mode, the interface remains active and conversion results may be clocked out after the max148/max149 enter a software power-down. the first logical 1 on din is interpreted as a start bit and powers up the max148/max149. following the start bit, the data input word or control byte also determines clock mode and power-down states. for example, if the din word con - tains pd1 = 1, then the chip remains powered up. if pd0 = pd1 = 0, a power-down resumes after one conversion. hardware power-down pulling shdn low places the converter in hardware pow - er-down (table 6). unlike software power-down mode, the conversion is not completed; it stops coincidentally with shdn being brought low. shdn also controls the clock frequency in internal clock mode. leaving shdn uncon - nected sets the internal clock frequency to 1.8mhz. when returning to normal operation with shdn unconnected, there is a t rc delay of approximately 2m i x c l , where c l is the capacitive loading on the shdn pin. pulling shdn high sets internal clock frequency to 225khz. this feature eases the settling-time requirement for the reference volt - age. with an external reference, the max148/max149 can be considered fully powered up within 2 f s of actively pulling shdn high. power-down sequencing the max148/max149 auto power-down modes can save considerable power when operating at less than maximum sample rates. figures 13, 14a, and 14b show the average supply current as a function of the sampling rate. the following discussion illustrates the various power-down sequences. lowest power at up to 500 conversions/channel/second the following examples show two different power-down sequences. other combinations of clock rates, compen - sation modes, and power-down modes may give lowest power consumption in other applications. figure 14a depicts the max149 power consumption for one or eight channel conversions utilizing full power- down mode and internal-reference compensation. a 0.01 f f bypass capacitor at refadj forms an rc filter with the internal 20k i reference resistor with a 0.2ms time constant. to achieve full 10-bit accuracy, 8 time constants or 1.6ms are required after power-up. waiting this 1.6ms in fastpd mode instead of in full power-up can reduce power consumption by a factor of 10 or more. this is achieved by using the sequence shown in figure 15. figure 14b. max149 supply current vs. conversion rate, fastpd figure 14c. typical reference-buffer power-up delay vs. time in shutdown average supply current vs. conversion rate (using fastpd) max148/9-f14b conversion rate (hz) average supply current (a) 100k 10k 1k 100 10 1 0 100 1000 10,000 1 0.1 1m r load = code = 1010101000 8 channels 1 channel typical reference-buffer power-up delay vs. time in shutdown max148/9-f14c time in shutdown (s) power-up delay (ms) 1 0.1 0.01 0.5 1.0 1.5 2.0 0 0.001 10 +2.7v to +5.25v, low-power, 8-channel, serial 10-bit adcs max148/max149 18 _____________________________________________________________________________________ lowest power at higher throughputs figure 14b shows the power consumption with external- reference compensation in fast power-down, with one and eight channels converted. the external 4.7 f f com - pensation requires a 75 f s wait after power-up with one dummy conversion. this graph shows fast multichannel conversion with the lowest power consumption possible. full power-down mode may provide increased power savings in applications where the max148/max149 are inactive for long periods of time, but where intermittent bursts of high-speed conversions are required. internal and external references the max149 can be used with an internal or external reference voltage, whereas an external reference is required for the max148. an external reference can be connected directly at vref or at the refadj pin. an internal buffer is designed to provide 2.5v at vref for both the max149 and the max148. the max149s internally trimmed 1.21v reference is buffered with a 2.06 gain. the max148s refadj pin is also buffered with a 2.00 gain to scale an external 1.25v reference at refadj to 2.5v at vref. internal reference (max149) the max149s full-scale range with the internal refer - ence is 2.5v with unipolar inputs and q 1.25v with bipolar inputs. the internal reference voltage is adjustable to q 1.5% with the circuit in figure 16. external reference with both the max149 and max148, an external refer - ence can be placed at either the input (refadj) or the output (vref) of the internal reference-buffer amplifier. the refadj input impedance is typically 20k i for the max149, and higher than 100k i for the max148. at vref, the dc input resistance is a minimum of 18k i . during conversion, an external reference at vref must figure 15. max149 fullpd/fastpd power-up sequence figure 16. max149 reference-adjust circuit figure 17. unipolar transfer function, full scale (fs) = vref + com, zero scale (zs) = com 1 0 0 din refadj vref 1.21v 0 2.50v 0 1 0 1 1 1 1 1 0 0 1 0 1 fullpd fastpd nopd fullpd fastpd t buffen = 75fs h = rc = 20ki x c refadj (zeros) ch1 ch7 (zeros) complete conversion sequence 1.6ms wait +3.3v refadj 510ki 24ki 100ki 0.01f 12 max149 output code full-scale transition transition 11...111 11...110 11...101 00...011 00...010 00...001 00...000 1 2 3 0 (com) fs fs - 3/2 lsb fs = vref + com zs = com input voltage (lsb) 1 lsb = vref 1024 +2.7v to +5.25v, low-power, 8-channel, serial 10-bit adcs max148/max149 ______________________________________________________________________________________ 19 deliver up to 350 f a dc load current and have 10 i or less output impedance. if the reference has a higher out - put impedance or is noisy, bypass it close to the vref pin with a 4.7 f f capacitor. using the refadj input makes buffering the external reference unnecessary. to use the direct vref input, disable the internal buffer by tying refadj to v dd . in power-down, the input bias current to refadj is typically 25 f a (max149) with refadj tied to v dd . pull refadj to agnd to minimize the input bias current in power-down. transfer function table 7 shows the full-scale voltage ranges for unipolar and bipolar modes. the external reference must have a temperature coef - ficient of 20ppm/ n c or less to achieve accuracy to within 1 lsb over the 0 n c to +70 n c commercial temperature range. figure 17 depicts the nominal, unipolar input/output (i/o) transfer function, and figure 18 shows the bipolar input/output transfer function. code transitions occur halfway between successive-integer lsb values. output coding is binary, with 1 lsb = 2.44mv (2.500v/1024) for unipolar operation, and 1 lsb = 2.44mv [(2.500v/2 - -2.500v/2)/1024] for bipolar operation. table 7. full scale and zero scale figure 18. bipolar transfer function, full scale (fs) = vref/2 + com, zero scale (zs) = com figure 19. power-supply grounding connection unipolar mode bipolar mode full scale zero scale positive full scale zero scale negative full scale vref + com com vref/2 + com com -vref/2 + com 011 . . . 111 011 . . . 110 000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 100 . . . 000 - fs com* input voltage (lsb) output code zs = com +fs - 1lsb *com vref/2 + com fs = vref 2 -fs = + com -vref 2 1lsb = vref 1024 +3v +3v gnd supplies dgnd +3v dgnd com agnd v dd digital circuitry r* = 10? *optional max148 max149 +2.7v to +5.25v, low-power, 8-channel, serial 10-bit adcs max148/max149 20 _____________________________________________________________________________________ layout, grounding, and bypassing for best performance, use pcbs. wire-wrap boards are not recommended. board layout should ensure that digital and analog signal lines are separated from each other. do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the adc package. figure 19 shows the recommended system ground con - nections. establish a single-point analog ground (star ground point) at agnd, separate from the logic ground. connect all other analog grounds and dgnd to the star ground. no other digital system ground should be con - nected to this ground. for lowest-noise operation, the ground return to the star grounds power supply should be low impedance and as short as possible. high-frequency noise in the v dd power supply may affect the high-speed comparator in the adc. bypass the supply to the star ground with 0.1 f f and 1 f f capaci - tors close to pin 20 of the max148/max149. minimize capacitor lead lengths for best supply-noise rejection. if the power supply is very noisy, a 10 i resistor can be connected as a lowpass filter (figure 19). figure 20. max148/max149 qspi connections, external reference figure 21. max148/max149-to-tms320 serial interface 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 mc683xx ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com v dd sclk din sstrb dout dgnd agnd refadj vref (power supplies) sck pcs0 mosi miso 0.1f 1f (gnd) 0.1f analog inputs +3v +3v +2.5v max148 max149 shdn cs xf clkx clkr dx dr fsr sclk din dout sstrb tms320lc3x cs max148 max149 +2.7v to +5.25v, low-power, 8-channel, serial 10-bit adcs max148/max149 ______________________________________________________________________________________ 21 high-speed digital interfacing with qspi the max148/max149 can interface with qspi using the circuit in figure 20 (f sclk = 2.0mhz, cpol = 0, cpha = 0). this qspi circuit can be programmed to do a conver - sion on each of the eight channels. the result is stored in memory without taxing the cpu, since qspi incorpo - rates its own microsequencer. the max148/max149 are qspi compatible up to the maximum external clock frequency of 2mhz. tms320lc3x interface figure 21 shows an application circuit to interface the max148/max149 to the tms320 in external clock mode. the timing diagram for this interface circuit is shown in figure 22. use the following steps to initiate a conversion in the max148/max149 and to read the results: 1) the tms320 should be configured with clkx (trans - mit clock) as an active-high output clock and clkr (tms320 receive clock) as an active-high input clock. clkx and clkr on the tms320 are tied together with the max148/max149s sclk input. 2) the max148/max149s cs pin is driven low by the tms320s xf_ i/o port to enable data to be clocked into the max148/max149s din. 3) an 8-bit word (1xxxxx11) should be written to the max148/max149 to initiate a conversion and place the device into external clock mode. see table 1 to select the proper xxxxx bit values for your specific application. 4) the max148/max149s sstrb output is monitored through the tms320s fsr input. a falling edge on the sstrb output indicates that the conversion is in progress and data is ready to be received from the max148/max149. 5) the tms320 reads in one data bit on each of the next 16 rising edges of sclk. these data bits rep - resent the 10 + 2-bit conversion result followed by 4 trailing bits, which should be ignored. 6) pull cs high to disable the max148/max149 until the next conversion is initiated. figure 22. tms320 serial-interface timing diagram sclk din sstrb dout start sel2 sel1 sel0 uni/bip sgl/dif pd1 pd0 msb b8 s1 s0 high impedance high impedance cs +2.7v to +5.25v, low-power, 8-channel, serial 10-bit adcs max148/max149 22 _____________________________________________________________________________________ ordering information (continued) pin configuration ? contact factory for availability of alternate surface-mount package. specify lead-free by placing + by the part number when ordering. * contact factory for availability of cerdip package, and for processing to mil-std-883b. not available in lead-free. package type package code document no. 20 plastic dip p20-4 21-0043 20 ssop a20-1 21-0056 20 cerdip j20-2 21-0045 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. top view 1 cho ch1 ch2 ch3 ch4 ch5 ch6 ch7 com shdn v dd sclk cs din sstrb dout dgnd agnd refadj vref 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 max148 max149 dip/ssop part ? temp range pin- package inl (lsb) max148aepp -40c to +85c 20 plastic dip 1/2 max148bepp -40c to +85c 20 plastic dip 1 max148aeap -40c to +85c 20 ssop 1/2 MAX148BEAP -40c to +85c 20 ssop 1 max148amjp -55c to +125c 20 cerdip* 1/2 max148bmjp -55c to +125c 20 cerdip* 1 max149 acpp 0c to +70c 20 plastic dip 1/2 max149bcpp 0c to +70c 20 plastic dip 1 max149acap 0c to +70c 20 ssop 1/2 max149bcap 0c to +70c 20 plastic dip 1 max149aepp -40c to +85c 20 plastic dip 1/2 max149bepp -40c to +85c 20 plastic dip 1 max149aeap -40c to +85c 20 ssop 1/2 max149beap -40c to +85c 20 ssop 1 max149amjp -55c to +125c 20 cerdip* 1/2 max149bmap/pr -55c to +125c 20 ssop 1 max149bmap/pr2 -55c to +125c 20 ssop 1 max149bmap/pr3 -55c to +125c 20 ssop 1 max149bmjp -55c to +125c 20 cerdip* 1 +2.7v to +5.25v, low-power, 8-channel, serial 10-bit adcs max148/max149 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 23 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 3 5/09 revised ordering information , electrical characteristics table, pin description , figure 9, added ruggedized plastic information. 1C4, 7, 13, 14, 16, 17, 22C23 4 1/10 revised ordering information . 22 |
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